This invention relates to a clock generating device, a circuit board, an image forming apparatus, and the method of generating a clock, and in particular, to the control of the rise and fall of a clock pulse at an arbitrary timing.
A clock is necessary for the circuit operation in various kinds of digital circuits. This clock is generated by a clock generating circuit of any one of various types.
In a clock generating circuit which has been heretofore put in practice, the cycle (frequency) of a clock is constant, and the positions of the leading edge and the trailing edge are fixed.
Regarding the above-mentioned clock, it has become a problem that an electromagnetic wave having its peak intensity at the clock frequency is radiated to the outside of the apparatus. Therefore, it has been developed a technology to lower the level of the peak portion by broadening the frequency band of the radiated electromagnetic wave through the frequency modulation of the clock (clock dithering).
For the above-mentioned, an IC to make frequency modulation of a clock by a PLL circuit has been put on the market.
Incidentally, by carrying out the above-mentioned clock dithering, the leading edge and trailing edge of a clock are made advanced or delayed as compared to a conventional clock which is not subjected to clock dithering. This is a phenomenon called clock slip. This clock slip is difficult to precisely control or to precisely measure. For this reason, it has been necessary to avoid a mixed use of a clock having been subjected to clock dithering and a clock having not been subjected to it because they have different phases and polarities from each other.
This invention has been made in order to solve the above-mentioned problem, and it is an object of the invention to provide a clock generating device, a circuit board, an image forming apparatus, and the method of generating a clock which are capable of controlling the leading edge and trailing edge of a clock to come to an arbitrary position for every clock pulse.
The above-mentioned problem can be solved by any one of the following means.
(1) A clock generating device comprising a clock generating section for generating a plurality of clocks having different phases respectively, and a selecting section for selecting some one out of said plurality of clocks to output it and switching the clock to a different one to output it within one cycle of the clock to be outputted.
(2) A clock generating device comprising a clock generating section for generating a plurality of clocks having different phases respectively, and a selecting section for combining at least two clocks having different phases respectively out of said plurality of clocks to output the composite one within one cycle of the clock to be outputted.
(3) A clock generating device comprising a clock generating section for generating a plurality of clocks having different phases respectively, and a selecting section for selecting some one out of said plurality of clocks to output it, wherein it is judged which one of the clocks is to be selected within one cycle of the clock to be outputted from said selecting section.
(4) A clock generating device comprising a clock generating section for generating a plurality of clocks having different phases respectively, and a selecting section for selecting some one out of said plurality of clocks on the basis of a selection signal to output it and selecting different clocks respectively for the leading edge and for the trailing edge within one cycle of the clock to be outputted.
(5) A clock generating device comprising a clock generating section for generating a plurality of clocks having different phases respectively, a selecting section for selecting some one out of said plurality of clocks on the basis of a selection signal to output it, and a switching control section for outputting a selection signal to said selecting section within one cycle of the clock to be outputted from said selecting section.
(6) A clock generating device as set forth in the paragraph (5), wherein the aforesaid switching control section generates a selection signal indicating which one is to be selected out of the plural clocks on the basis of output clock information set beforehand to output it to said selecting section.
(7) A clock generating device as set forth in the paragraph (6), further comprising a synchronized signal detecting section for detecting the state of phase difference of the plural clocks outputted from the aforesaid clock generating section, wherein the aforesaid switching control section generates a selection signal indicating which one is to be selected out of the plural clocks on the basis of output clock information set beforehand and the state of phase difference detected by said synchronized signal detecting section to output it to the aforesaid selecting section.
(8) A clock generating device as set forth in the paragraph (6) or (7), wherein the aforesaid output clock information is memorized beforehand in a memory section or is set by an operation circuit.
(9) A clock generating device as set forth in any one of the paragraphs (1) to (8), wherein when the clock which is outputted from the aforesaid selecting section is switched over from one of the plural clocks to another clock, said one clock and said another clock are in the state of the same logic.
(10) A clock generating device as set forth in any one of the paragraphs (1) to (9), wherein the aforesaid clock generating section comprises a delay chain portion for generating a plurality of delayed clocks having different phases respectively.
(11) A clock generating device as set forth in any one of the paragraphs (1) to (9), further comprising a basic clock generating section for generating a tuned basic clock, wherein the aforesaid clock generating section comprises a delay chain portion for generating a plurality of delayed clocks having different phases respectively by delaying the basic clock outputted from said basic clock generating section.
(12) A clock generating device as set forth in the paragraph (11), wherein the aforesaid selecting section selects some one out of the aforesaid basic clock outputted from the aforesaid basic clock generating section and the aforesaid plural delayed clocks outputted from the aforesaid clock generating section.
(13) A clock generating device which outputs a dithering clock being in the state of a diffused frequency band through dispersing the cycle of the clock to be outputted against the basic clock inputted, wherein said dithering clock is generated by using a plurality of clocks having different phases respectively.
(14) A clock generating device as set forth in the paragraph (13), further comprising a basic clock generating section for generating a tuned basic clock, wherein the aforesaid plural clocks having different phases respectively are generated by delaying the basic clock outputted from said basic clock generating section.
(15) A clock generating device as set forth in any one of the paragraphs (1) to (14) which is made up of an integrated circuit.
(16) A clock generating device as set forth in the paragraph (15) which is made up of a digital circuit.
(17) A circuit board provided with a clock generating device as set forth in any one of the above paragraphs (1) to (16).
(18) An image forming apparatus which is controlled by using a clock outputted from a clock generating device as set forth in any one of the above paragraphs (1) to (16).
(19) The method of generating a clock in which some one is selected out of a plurality of clocks having different phases respectively to be outputted and it is switched over to a different clock within one cycle of the clock to be outputted.